Now about something different: SPI.

A weak point of the 6502 is, that it was invented before there was SPI.
6502 won't be too efficient when Bit_banging a SPI interface
by software only...
So I spent some thoughts about how to give the CPU a SPI interface.

SPI mode 3, that is.

First we need a "free" opcode for implementing SPI functionality,
and I would suggest to use COP, $02.

Now concepts for two different approaches of implementation:
1) an instruction similar to ROL A for shifting one Bit
2) an instruction that shifts 8 Bits.

I'm not sure if we can afford to have the additional hardware
in the design... nevertheless I wanted to share my thoughts.

;---

1) an instruction similar to ROL A for shifting one Bit (which takes 2 cycles)

SPI clock would have half the speed of PHI2.

Hardware cost: four NAND gates (74132) plus one inverter.

Timing:
[code]
|instruction| immediate |instruction|           |instruction|
|fetch: ADC#| value     |fetch: SPI |           |fetch: SPI |
|-----------|-----------|-----------|-----------|-----------|
                                    .           .           .
                             -------------       -------------
                             SCLK   .     |     |           .
                                    .      -----.           .
                             ------- ----------------------- -
                             MOSI   |           .           |
                             ------- ----------------------- -
                             ------- ----------------------- -
                             MISO   |           . ALU ROL A |
                             ------- ----------------------- -
                                                *           *
                                                |           |
                                              MISO          A
                                           is sampled    changes
                                              here        here
[/code]
In this example, an ADC# is executed before the SPI instruction.
The ADC add is done in parallel with the next instruction fetch,
so A changes after the falling edge of PHI2.

MOSI simply is Bit 7 of the A shadow register.

We now just take an unused output of the read decoder and label it SPI,
this is possible because there is no ALU activity in the cycle
that follows the SPI instruction fetch.

SCLK should be low in that cycle, but since we could expect
a glitch in the decoder output maybe 50ns after the falling
edge of PHI2, it would be better to send SPI and /PHI11
(the CPU internal equivalent of PHI2) into a NAND gate
for generating SCLK.
Downside is, that SCLK won't be symmetrical,
but I think we can live with that.
(Ok, so it's another kludge...)

MISO has to be sampled at the rising edge of SCLK,
in other words: at the end of this cycle.
I think the best approach to this would be to sample MISO
into the temporary carry flag which is used for address calculation.
For doing this, we need to have a 2:1 multiplexer in front
of the flipflop input that routes either ALU carry output
or MISO into the flipflop controlled by the SPI signal
from the decoder.
This would require 3 NAND gates and an inverter.

In the next cycle (in parallel to the next instruction fetch),
the ALU does a ROL A with the carry from the temporary carry flag,
and that's all.

;---

2) an instruction that shifts 8 Bits (which takes 8 cycles)

SPI clock would have the same speed as PHI2.

Timing: IF means 'instruction fetch'.
[code]
|IF   |                                         |IF   |
|SPI  |                                         |NOP  |
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
      .     .     .     .     .     .     .     .     .
    -----    --    --    --    --    --    --    --    ------
SCLK     |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
          --    --    --    --    --    --    --    --
     ---- ----- ----- ----- ----- ----- ----- ----- ---------
MOSI     | A.7 | A.6 | A.5 | A.4 | A.3 | A.2 | A.1 | A.0
     ---- ----- ----- ----- ----- ----- ----- ----- ---------
     ---- ----- ----- ----- ----- ----- ----- ----- ---------
MISO     |     |     |     |     |     |     |     |
     ---- ----- ----- ----- ----- ----- ----- ----- ---------
            *     *     *     *     *     *     *     *
            |            
           MISO           
        is sampled           
           here            
[/code]

For generating MOSI, we need to route A shadow register Bit 7
through a 7474 flipflop clocked by the rising edge of /PHI11
(the rising edge of PHI2, that is).

Again we need a control signal labeled 'SPI,
maybe it would be a special case of "read A" or "write A".
...That's the problem.

Again, SCLK is generated with a NAND gate fed by /PHI11 and SPI.

In those 8 cycles where the ALU does a ROL A,
MISO needs to be routed directy to the carry input of the ALU,
and that's all.
I think that the propagation delay MISO to W bus isn't critical,
but we better keep an eye on that...

;------

Delaying the SCL output by half a SCLK cycle would turn
SPI mode 3 into SPI mode 2.

After that, inverting the SCLK output would turn
mode 3 into mode 1, and mode 2 into mode 0.

;---
[url]elm-chan.org/docs/spi_e.html[/url]
;---

Cheers,
Dieter.


